module rx(clk,rst,hl_sig,Rx_pin_in,bps_clk,Rx_en,count_sig,rx_data,end_sig);
input clk,rst,hl_sig,Rx_pin_in,Rx_en,bps_clk;
output count_sig,end_sig;
output[7:0] rx_data;
reg[3:0] i=0;
reg[7:0] data=0;
reg count=0;
reg done=0;

always @(posedge clk or negedge rst)
begin
	if(!rst)
	begin
		i<=0;
		data<=0;
		count<=0;
		done<=0;
	end
	else if(Rx_en)
			case(i)
		          4'd0:if(hl_sig) begin i<=i+1'b1; count<=1'b1; end
					 4'd1: if(bps_clk) begin i<=i+1'b1; end
					 4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9:
					 if(bps_clk) begin i<=i+1'b1; data[i-2]<=Rx_pin_in; end
					 //4'd10:if(bps_clk) begin i<=i+1'b1; end
					 //4'd11:if(bps_clk) begin i<=i+1'b1; end
					 4'd10:begin i<=i+1'b1; done<=1'b1; count<=1'b0; end
					 4'd11:begin i<=4'd0; done<=1'b0; end
				 endcase
end
assign count_sig=count;
assign rx_data=data;
assign end_sig=done;
endmodule